Area-Efficient Evaluation of Arithmetic Expressions Using Deeply Pipelined Floating-Point Cores

Due to technological advances, it has become possible to implement floating-point cores on FPGAs in an effort to provide hardware acceleration for the myriad applications that require high performance floating-point arithmetic. However, in order to achieve a high clock rate, these floating-point cores must be deeply pipelined. Due to this deep pipelining and the complexity of floating-point arithmetic, floating-point cores use a great deal of the FPGA’s area. It is thus important to use as few floating-point cores in an architecture as possible. However, the deep pipelining makes it difficult to reuse the same floatingpoint core for a series of floating-point computations that are dependent upon one another. In this paper, we describe an area-efficient architecture and algorithm for the evaluation of arithmetic expressions. This design effectively hides the pipeline latency of the floating-point cores and uses only one floating-point core for each type of operator in the expression. The design is applicable to a wide variety of fields such as scientific computing, cognition, and graph theory. We analyze the performance of this design when implemented on a Xilinx Virtex-II Pro FPGA. Focus Session—Reconfigurable Supercomputing